Acorn Econet Bridge Variant 1 Memory Map

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Addresses outside the ROM used by Acorn Econet Bridge Variant 1 at run time — zero-page workspace, RAM buffers, and memory-mapped I/O. For the code that lives at &E000 upward, see the disassembly listing.

Zero page

Address	Name	Access	Description
`&0000`	`st_ptr_lo`	R/W	Low byte of the self-test scan pointer. Paired with `st_ptr_hi` to form a 16-bit indirect pointer walked by `self_test_rom_checksum` and `self_test_ram_pattern`. Also used as an anti-aliasing tripwire byte (the `INC $00`) in `ram_test`, and as a scratch victim byte during `self_test_zp` when the zero-page itself is under test.
`&0001`	`st_ptr_hi`	R/W	High byte of the self-test scan pointer. Paired with `st_ptr_lo`; incremented page by page as the scanning loops stride through each 256-byte block of ROM or RAM. Also a scratch victim byte during `self_test_zp`.
`&0002`	`st_page_count`	R/W	Page counter for the self-test scans. Pre-loaded with a hard-coded `&20` (32 pages = 8 KiB) at every site and decremented once per page by `self_test_rom_checksum`, `self_test_ram_pattern`, and both phases of `self_test_ram_incr`. The self-test therefore always covers exactly the low 8 KiB of RAM (`&0000-&1FFF`) and the 8 KiB ROM (`&E000-&FFFF`), regardless of what the boot-time `ram_test` found: this counter is never loaded from `top_ram_page`. Also a scratch victim byte during `self_test_zp`.
`&0003`	`st_pass_phase`	R/W	Self-test pass-phase flag. Initialised by `self_test` at entry and toggled by `self_test_pass_done` at the end of each full pass; bit 7 then selects between a plain restart from `self_test_reset_adlcs` and the alternate path through `self_test_alt_pass`, which drives the ADLC control registers slightly differently to catch intermittent faults.
`&0080`	`mem_ptr_lo`	R/W	Low byte of the indirect pointer. Paired with `mem_ptr_hi`. Used by `ram_test` to scan memory upward one page at a time, and by the TX/RX byte loops in the frame handlers, e.g. `transmit_frame_a`.
`&0081`	`mem_ptr_hi`	R/W	High byte of the indirect pointer. Paired with `mem_ptr_lo`.
`&0082`	`top_ram_page`	R/W	Highest page that verified `&AA`/`&55` during `ram_test`. Used later by workspace initialisation to decide how much RAM is safe to touch.

RAM workspace

Address	Name	Access	Description
`&0200`	`tx_end_lo`	R/W	Low byte of the TX end-pointer, consumed by `transmit_frame_a`. The TX loop sends byte pairs from `mem_ptr_lo` upward and terminates once the index reaches or passes this pointer.
`&0201`	`tx_end_hi`	R/W	High byte of the TX end-pointer. Paired with `tx_end_lo`.
`&0214`	`ctr24_lo`	R/W	Low byte of a 24-bit counter reused by several routines. `wait_adlc_a_idle` uses all three bytes as a timeout; `stagger_delay` uses this low byte alone as an 8-bit delay.
`&0215`	`ctr24_mid`	R/W	Middle byte of the 24-bit counter. Rooted at `ctr24_lo`.
`&0216`	`ctr24_hi`	R/W	High byte of the 24-bit counter. Rooted at `ctr24_lo`.
`&0228`	`rx_len`	R/W	Byte count received into the RX frame buffer. Written by the drain loop once the ADLC reports end-of-frame; read back by the dispatch paths to decide how many payload bytes to process.
`&0229`	`announce_flag`	R/W	Event-driven re-announcement selector. Set by `rx_a_handle_80` / `rx_b_handle_80` to `&40` (side A selected) or `&80` (side B) when a peer bridge's `BridgeReset` scout arrives. Cleared in `re_announce_done` once all ten `BridgeReply` frames have been emitted. Polled by `main_loop_idle`; the entire re-announcement state machine is quiescent while this byte is zero.
`&022A`	`announce_tmr_lo`	R/W	Low byte of the 16-bit re-announcement countdown. Decremented every pass through `main_loop_idle`; fires `re_announce` when it reaches zero.
`&022B`	`announce_tmr_hi`	R/W	High byte of the 16-bit re-announcement countdown. Paired with `announce_tmr_lo`.
`&022C`	`announce_count`	R/W	Remaining `BridgeReply` frames to emit in the current re-announcement burst. Initialised to 10 when a peer `BridgeReset` is heard, decremented in `re_announce`, and clears `announce_flag` on reaching zero.

RAM buffers

Address	Name	Access	Description
`&023C`	`rx_dst_stn`	R/W	RX frame buffer byte 0 – destination station number. First byte of the 20-byte RX staging area at `&023C-&024F` filled by `rx_frame_a` / `rx_frame_b`.
`&023D`	`rx_dst_net`	R/W	RX frame buffer byte 1 – destination network number.
`&023E`	`rx_src_stn`	R/W	RX frame buffer byte 2 – source station number.
`&023F`	`rx_src_net`	R/W	RX frame buffer byte 3 – source network number.
`&0240`	`rx_ctrl`	R/W	RX frame buffer byte 4 – control byte. Bridge protocol uses `&80`..`&83`; see `rx_frame_a_dispatch`.
`&0241`	`rx_port`	R/W	RX frame buffer byte 5 – port number. The bridge-protocol port is `&9C`.
`&0248`	`rx_query_port`	R/W	RX frame buffer byte 12 – port on which the querier wants the bridge to send its response.
`&0249`	`rx_query_net`	R/W	RX frame buffer byte 13 – network number that a `ctrl=&83` (IsNet) query is asking about. Checked against `reachable_via_b` / `reachable_via_a` in the query handlers.
`&025A–&0359`	`reachable_via_b`	R/W	256-byte routing table for forwarding out of side B. Indexed by destination network number; a non-zero entry means "this network is reachable from here". Consulted by `rx_frame_a`. Initialised with `net_num_b` (our own side-B network, directly reachable) and 255 (broadcast), then extended by bridge-announcement messages received on side A.
`&035A–&0459`	`reachable_via_a`	R/W	256-byte routing table for forwarding out of side A. Indexed by destination network number; a non-zero entry means "this network is reachable from here". Consulted by `rx_frame_b`. Initialised with `net_num_a` (our own side-A network, directly reachable) and 255 (broadcast), then extended by bridge-announcement messages received on side B.
`&045A`	`tx_dst_stn`	R/W	TX frame buffer byte 0 – destination station number. First byte of the outbound frame staging area at `&045A-&0460+`, populated by the frame-builder subroutines and consumed by `transmit_frame_a` / `transmit_frame_b`.
`&045B`	`tx_dst_net`	R/W	TX frame buffer byte 1 – destination network number.
`&045C`	`tx_src_stn`	R/W	TX frame buffer byte 2 – source station number.
`&045D`	`tx_src_net`	R/W	TX frame buffer byte 3 – source network number.
`&045E`	`tx_ctrl`	R/W	TX frame buffer byte 4 – control byte in a scout frame, or the first data byte in a data frame. The same buffer serves both frame types; the caller chooses the semantics.
`&045F`	`tx_port`	R/W	TX frame buffer byte 5 – port in a scout frame, or the second data byte in a data frame. Pair with `tx_ctrl`.
`&0460`	`tx_data0`	R/W	TX frame buffer byte 6 – first optional scout payload byte. For example, a queried network number in a `WhatNet` response.

I/O — side A

Address	Name	Access	Description
`&C000`	`net_num_a`	R	Econet side A network number, read at `&C000`. Sourced from a bank of jumpered links buffered by a 74LS244. 7-bit (range 1-127); the top link is always made, so bit 7 reads 0. The Bridge has no station number of its own – it sits on each Econet segment as a promiscuous receiver and broadcaster.
`&C800`	`adlc_a_cr1`	R/W	ADLC A control/status port 0. Write: CR1 (or CR3 when AC=1 in CR1). Read: SR1. IRQ summary is in SR1 bit 7; `wait_adlc_a_irq` spins on it.
`&C801`	`adlc_a_cr2`	R/W	ADLC A control/status port 1. Write: CR2 (or CR4 when AC=1). Read: SR2.
`&C802`	`adlc_a_tx`	R/W	ADLC A TX/RX FIFO port. Write: push a byte into the TX FIFO (frame continues). Read: pop a byte from the RX FIFO.
`&C803`	`adlc_a_tx2`	W	ADLC A TX-last-byte port. Write: push the final byte of a frame (chip closes the frame and appends the FCS + flag). Reading this port is not used by the Bridge.

I/O — side B

Address	Name	Access	Description
`&D000`	`net_num_b`	R	Econet side B network number, read at `&D000`. Sourced from a bank of jumpered links buffered by a 74LS244. 7-bit (range 1-127); the top link is always made, so bit 7 reads 0. Paired with `net_num_a` on the opposite segment.
`&D800`	`adlc_b_cr1`	R/W	ADLC B control/status port 0. Write: CR1 (or CR3 when AC=1 in CR1). Read: SR1. IRQ summary is in SR1 bit 7; `wait_adlc_b_irq` spins on it. CR3 bit 7 (reached via this port with AC=1) drives IC18's `~LOC/DTR` pin, which sinks the front-panel status LED. `self_test_reset_adlcs` lights it; `adlc_b_full_reset` extinguishes it.
`&D801`	`adlc_b_cr2`	R/W	ADLC B control/status port 1. Write: CR2 (or CR4 when AC=1). Read: SR2.
`&D802`	`adlc_b_tx`	R/W	ADLC B TX/RX FIFO port. Write: push a byte into the TX FIFO (frame continues). Read: pop a byte from the RX FIFO.
`&D803`	`adlc_b_tx2`	W	ADLC B TX-last-byte port. Write: push the final byte of a frame (chip closes the frame and appends the FCS + flag). Reading this port is not used by the Bridge.